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| TUESDAY, June 8, 2004, 10:30 AM - 12:00 PM | Room: 6C |
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TOPIC AREA: PHYSICAL CIRCUIT DESIGN
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SESSION 3
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| Clock Routing and Buffering
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| Chair: John Lillis - Univ. of Illinois, Chicago, IL
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| Organizers: Dirk Stroobandt, Raymond Nijssen
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| This session presents three papers on clock routing and buffering that address critical design challenges in today's deep sub-micron regime. The first paper shows how to add cross links to current clock tree routing constructions to reduce variability. The next paper presents a fast buffering technique that can handle a variety of physical environment constraints. The last paper in the session presents a method for choosing repeaters that minimize power while maintaining excellent daley characteristics, which is becoming an increasingly prevalent problem.
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| 3.1 |
Reducing Clock Skew Variability via Cross Links
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| Speaker(s): | Anand Rajaram - Texas A&M Univ., College Station, TX
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| Author(s): | Anand Rajaram - Texas A&M Univ., College Station, TX
Jiang Hu - Texas A&M Univ., College Station, TX
Rabi Mahapatra - Texas A&M Univ., College Station, TX
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| 3.2 | Fast and Flexible Buffer Trees That Navigate the Physical Layout Environment |
| Speaker(s): | Milos Hrkic - Univ. of Illinois, Chicago, IL
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| Author(s): | Charles J. Alpert - IBM Corp., Austin, TX
Milos Hrkic - Univ. of Illinois, Chicago, IL
Jiang Hu - Texas A&M Univ., College Station, TX
Stephen T. Quay - IBM Corp., Austin, TX
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| 3.3 | Practical Repeater Insertion For Low Power: What Repeater Library Do We Need? |
| Speaker(s): | Xun Liu - North Carolina State Univ., Raleigh, NC
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| Author(s): | Xun Liu - North Carolina State Univ., Raleigh, NC
Yuantao Peng - North Carolina State Univ., Raleigh, NC
Marios C. Papaefthymiou - Univ. of Michigan, Ann Arbor, MI
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