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TUESDAY, June 8, 2004, 10:30 AM - 12:00 PM | Room: 6C
TOPIC AREA:  PHYSICAL CIRCUIT DESIGN

   SESSION 3
  Clock Routing and Buffering
  Chair: John Lillis - Univ. of Illinois, Chicago, IL
  Organizers: Dirk Stroobandt, Raymond Nijssen

  This session presents three papers on clock routing and buffering that address critical design challenges in today's deep sub-micron regime. The first paper shows how to add cross links to current clock tree routing constructions to reduce variability. The next paper presents a fast buffering technique that can handle a variety of physical environment constraints. The last paper in the session presents a method for choosing repeaters that minimize power while maintaining excellent daley characteristics, which is becoming an increasingly prevalent problem.

    3.1   Reducing Clock Skew Variability via Cross Links
  Speaker(s): Anand Rajaram - Texas A&M Univ., College Station, TX
  Author(s): Anand Rajaram - Texas A&M Univ., College Station, TX
Jiang Hu - Texas A&M Univ., College Station, TX
Rabi Mahapatra - Texas A&M Univ., College Station, TX
    3.2Fast and Flexible Buffer Trees That Navigate the Physical Layout Environment
  Speaker(s): Milos Hrkic - Univ. of Illinois, Chicago, IL
  Author(s): Charles J. Alpert - IBM Corp., Austin, TX
Milos Hrkic - Univ. of Illinois, Chicago, IL
Jiang Hu - Texas A&M Univ., College Station, TX
Stephen T. Quay - IBM Corp., Austin, TX
    3.3Practical Repeater Insertion For Low Power: What Repeater Library Do We Need?
  Speaker(s): Xun Liu - North Carolina State Univ., Raleigh, NC
  Author(s): Xun Liu - North Carolina State Univ., Raleigh, NC
Yuantao Peng - North Carolina State Univ., Raleigh, NC
Marios C. Papaefthymiou - Univ. of Michigan, Ann Arbor, MI